The present invention relates to a ferroelectric random access memory (FeRAM) and, more particularly, to a method for forming the FeRAM using an aluminum oxide layer as an oxygen diffusion barrier.
A ferroelectric random access memory (FeRAM) is a nonvolatile semiconductor memory device with a highly integrated dynamic random access memory (DRAM), the speedy information processing of a static random access memory (SRAM), and the information storing function of a flash memory. As compared with a conventional flash memory and an electrically erasable programmable read only memory (EEPROM), it has a relatively low operational voltage and an operational speed that is about 1000 times faster.
When voltage is applied to a DRAM capacitor, which includes a dielectric layer such as a SiO2 layer or a SiON layer, and then the voltage supply is terminated, the charges in the DRAM capacitor are discharged so that data stored in the DRAM are lost.
Being different from the DRAM capacitor, a ferroelectric capacitor in the FeRAM maintains previously stored data by the remnant polarization of a ferroelectric material even if the power supply is terminated.
FIG. 1 is a circuit diagram illustrating a memory cell structure of a conventional FeRAM device including one transistor and one ferroelectric capacitor. A pass-gate transistor (Tr) is connected to a bit line (BL) and a capacitor (C), and the capacitor (C) functions as a charge storage element through a first electrode and a second electrode which are respectively connected to a plate line (PL) and the transistor (Tr). Also, a ferroelectric layer is formed between the first electrode and the second electrode.
The FeRAM device is similar to the DRAM device in that a capacitor and a transistor are connected to a word line and a plate line, respectively. However, the FeRAM device is different from the DRAM device in that the capacitor has a thin ferroelectric layer and the plate line is not connected to ground voltage or a fixed voltage, e.g., xc2xd Vcc, and each cell is connected to a separate plate line so that power can be applied to the separate plate line on a cell-by-cell basis.
FIG. 2 is a graph showing a hysteresis loop of a ferroelectric capacitor. In FIG. 2, positive voltage is defined when the potential of the plate line is higher than that of the bit line and remnant polarization at points xe2x80x9caxe2x80x9d and xe2x80x9ccxe2x80x9d, are defined to data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, respectively.
If the transistor is turned on and a negative voltage level is applied to the plate line xe2x80x9cPLxe2x80x9d, then a negative voltage is also applied to the ferroelectric capacitor and a charge variation passes through point xe2x80x9cdxe2x80x9d in the hysteresis loop. After that, in case of turning the applied voltage to xe2x80x9c0 Vxe2x80x9d, polarization value goes to point xe2x80x9caxe2x80x9d and the data xe2x80x9c1xe2x80x9d is stored. Meanwhile, a positive voltage level is applied to the ferroelectric capacitor, the charge variation passes through point xe2x80x9cbxe2x80x9d, a polarization value goes to point xe2x80x9ccxe2x80x9d by turning the applied voltage to xe2x80x9c0 Vxe2x80x9d and the data xe2x80x9c0xe2x80x9d is stored.
When the voltage is applied to the ferroelectric capacitor, data reading process is carried out by detecting a voltage variation on the bit line. That is, if a positive voltage is applied to the capacitor, in case the data is xe2x80x9c0xe2x80x9d, the charge variation of xcex94 Q0 is detected. That is, the charge variation on the bit line is determined by information stored on the capacitor.
The charge variation due to the remnant polarization of the ferroelectric capacitor changes a voltage level on the bit line. Typically, parasite capacitance xe2x80x9cCbxe2x80x9d exists on the bit line itself. When the transistor is turned on and a memory to be read out is selected, charges of as much as xcex94 Q1 or xcex94 Q0 are outputted. Bit line voltages xe2x80x9cV1xe2x80x9d and xe2x80x9cV0xe2x80x9d are acquired by dividing the xcex94 Q1 and the xcex94 Q0 with the sum of bit line capacitance (Cb) and ferroelectric capacitor (C) capacitance xe2x80x9cCsxe2x80x9d, respectively and these values are given by:
V1=xcex94 Q1/(Cb+Cs)
V0=xcex94 Q0/(Cb+Cs)
Therefore, the potential on the bit line is varied according to the difference between the data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d. When the transistor is turned on by applying a voltage level to the word line, the potential on the bit line is changed to the xe2x80x9cV1xe2x80x9d or the xe2x80x9cV0xe2x80x9d. In order to determine whether potential on the bit line is in a voltage level of xe2x80x9cV1xe2x80x9d or xe2x80x9cV0xe2x80x9d, a reference voltage (Vref), which is set to a specific voltage level between the voltage levels xe2x80x9cV1xe2x80x9d and xe2x80x9cV0xe2x80x9d, is used.
SrBi2Ta2O9 (hereinafter, referred to as an SBT), (Bi, La)4Ti3O12 (hereinafter, referred to as a BLT) or Pb(Zr, Ti)O3 (hereinafter, referred to as a PZT) thin layer is mainly used as a dielectric material in the FeRAM. Since a ferroelectric material is of crystallized structure, a bottom material disposed thereunder is important in growing the ferroelectric material. That is, in the ferroelectric capacitor, the electrode is largely affected by the ferroelectric characteristics, so there is a requirement for sufficiently low resistance, a small lattice mismatch between the ferroelectric material and the electrode, a high heat-resistance, a low reactivity, a high oxidation barrier characteristic and a good adhesion between the electrode and the ferroelectric material.
Especially, the ferroelectric memory device manufacturing process incorporates a high thermal process. Accordingly, a polysilicon layer, which has been used in a DRAM device, cannot be used as an electrode, because the polysilicon layer may be oxidized in forming a ferroelectric layer, such as the SBT, or in other thermal processes.
Therefore, in a conventional method, a metal layer is used as an interconnection layer in the FeRAM device, connecting a top electrode of the ferroelectric capacitor to a metal oxide semiconductor field effect transistor (MOSFET).
FIG. 3 is a cross sectional view showing a FeRAM device according to the prior art. A transistor having a gate insulating film 12, a gate electrode 13 and a source/drain region 14 is formed in a semiconductor substrate 10 where a field oxide layer 11 is formed. A first interlayer insulating film 15 is formed over the transistor and a tungsten or a polysilicon plug 16 is buried in a contact hole exposing the source/drain region 14 of the transistor through a selective etching process of the first interlayer insulating film 15. Also, an Ir oxidation barrier film 17 is formed on the plug 16 and a Si3N4 film spacer 18 is formed on the sidewalls of the Ir oxidation barrier film 17. A bottom electrode 19 of a ferroelectric capacitor is formed on the Ir oxidation barrier film 17 and the Si3N4 film spacer 18, and a ferroelectric film 20, a top electrode 21, and a second interlayer insulating film 22 are, in this order, formed on the entire structure. To form the ferroelectric film 20 for charge storage, a thermal treatment process is carried out at a high temperature of approximately 650xc2x0 C. to 750xc2x0 C. in an oxygen atmosphere. During this process, oxygen may penetrate into the ferroelectric film 20, the bottom electrode 19 and the Ir oxidation barrier film 17. If the plug 16, which forms an electrically connecting path between the capacitor and the transistor, is oxidized by the penetrating oxygen, the oxidized plug may cause an electrical disconnection between the capacitor and the transistor.
FIG. 4 is a cross sectional view showing oxygen oxidation paths (xe2x80x9caxe2x80x9d, xe2x80x9cbxe2x80x9d) in the prior art ferroelectric capacitor of FIG. 3. Although, in the prior stacked capacitor, the oxidation of the plug 16 in the vertical direction xe2x80x9caxe2x80x9d is prevented by using the Ir oxidation barrier film 17, the oxygen can easily penetrate into the plug 16 in the horizontal direction indicated by xe2x80x9cbxe2x80x9d through an interface between the Ir oxidation barrier film 17 and the first interlayer insulating film 15. Further the penetrating oxygen oxidizes a contacted part between the plug 16 and the Ir oxidation barrier 17.
Accordingly, a thermal treatment condition in order to crystallize the ferroelectric film is limited by the potential for oxidation of the plug. Typically, a furnace annealing is performed at a low temperature of about 650xc2x0 C. or a rapid thermal annealing is performed at a temperature of about 700xc2x0 C. in order to crystallize the ferroelectric film. However, because these thermal treatments cannot sufficiently crystallize the ferroelectric film, there is a problem in which the characteristics of the ferroelectric capacitor may deteriorate in the following processes.
It is, therefore, an object of the present invention to provide a ferroelectric random access memory (FeRAM) device using an aluminum oxide layer as an oxygen oxidation barrier and a method for forming the same.
In accordance with an aspect of the present invention, there is provided a FeRAM device comprising a semiconductor substrate; a transistor having a gate insulating film, a gate electrode and a source/drain region that are formed in the semiconductor substrate; a first interlayer insulating film formed over the transistor; a plug buried in a contact hole exposing the source/drain region of the transistor through a selective etching process of the first interlayer insulating film; a first oxidation barrier film formed on the plug and the first interlayer insulating film; a lateral oxidation barrier film formed on sidewalls of the first oxidation barrier film and on a portion of the first interlayer insulating film in order to prevent oxygen from diffusing into the interface therebetween; a bottom electrode formed on the first oxidation barrier film and the lateral oxidation barrier film; a ferroelectric film formed on the bottom electrode; a top electrode formed on the ferroelectric film; and a second interlayer insulating film formed on the entire structure.
In accordance with another aspect of the present invention, there is provided a ferroelectric random access memory (FeRAM) device comprising a semiconductor substrate; a transistor having a gate insulating film, a gate electrode and a source/drain region that are formed in the semiconductor substrate; a first interlayer insulating film formed over the transistor; a plug buried in a contact hole exposing the source/drain region of the transistor through a selective etching process of the first interlayer insulating film; an oxidation barrier film formed on the plug and the first interlayer insulating film; an aluminum oxide (Al2O3) oxidation barrier film formed on sidewalls of the oxidation barrier film and the first interlayer insulating film; a silicon nitride (Si3N4) oxidation barrier film formed on the aluminum oxide (Al2O3) oxidation barrier film; a bottom electrode formed on the aluminum oxide (Al2O3) oxidation barrier film and the silicon nitride (Si3N4) oxidation barrier film; a ferroelectric film formed on the bottom electrode; a top electrode formed on the ferroelectric film; and a second interlayer insulating film formed on the entire structure.
In accordance with still another aspect of the present invention, there is provided a method for fabricating a ferroelectric random access memory (FeRAM), comprising the steps of: a) forming a semiconductor substrate; b) forming a transistor having a gate insulating film, a gate electrode and a source/drain region that are formed in the semiconductor substrate; c) forming a first interlayer insulating film over the transistor; d) burying a plug in a contact hole exposing the source/drain region of the transistor through a selective etching process of the first interlayer insulating film; e) forming a first oxidation barrier film on the plug and the first interlayer insulating film; f) forming a lateral oxidation barrier film on sidewalls of the first oxidation barrier film and a portion of the first interlayer insulating film in order to prevent oxygen from diffusing into the interface therebetween; g) forming a bottom electrode on the first oxidation barrier film and lateral oxidation barrier film; h) forming a ferroelectric film on the bottom electrode; i) forming a top electrode on the ferroelectric thin film; and j) forming a second interlayer insulating film on the entire structure.